A Survey of Architectural Design and Implementation Tradeoffs in Network on Chip Systems

As the number of components on a given chip increase in this billion transistor era, System on Chip (SoC) architectures become ever more powerful. Key to this architecture is the ability to integrate multiple heterogeneous components into a single architecture, which requires modularity and abstraction. An integral part of this architectural design is the methods by which the various components communicate with one another. Network on Chip (NoC) architectures attempt to address these concerns by providing various component level architectures with specific interconnection network topologies and routing techniques. The choice of architecture, design, and routing strategy can have a large impact on performance, power dissipation, and efficient usage of area on the silicon chip. Discussed will be the affects of topological, architectural and routing design choices on overall efficiency and performance.